G - Physics – 11 – C
Patent
G - Physics
11
C
354/224, 354/241
G11C 29/00 (2006.01) G06F 11/00 (2006.01) G11C 29/20 (2006.01) G11C 29/44 (2006.01)
Patent
CA 1082368
ABSTRACT OF THE DISCLOSURE A system is provided for pretesting electronic memory locations and automatically identifying faulty memory sections. The system includes read/write memory means for storing a plurality of binary encoded words at a plurality of address locations, each word having at least two binary bits, the memory means initially being cleared to a condition in which all of the binary bits thereof should be of the same type; identifying means coupled with the memory means and responsive to a readout of the words stored therein for identifying a faulty bit of a word at any address location which is not cleared; addressing means for selecting different address locations in the memory means; and means coupled with the identifying means for causing the addressing means to select a new address location upon identification of a faulty bit by the identify- ing means. The system pretests all data bit locations for each address prior to the entry of any data into that address, and automatically skips an address having a faulty data bit location in it. In addition, the system functions, upon reading out of data information from the memory chips, uniquely to identify any faulty MOS RAM memory chip, so that such chip may be removed and replaced if desired. This system effectively prevents the entry of data into a faulty memory address location. It is capable of pinpointing the location of a faulty memory chip without requiring specific testing for faulty memory locations. The identification of the faulty memory chip is accomplished during normal operation of the system without disturbing the normal operation.
265752
Engineered Systems Inc.
Marcus & Associates
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