G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 11/36 (2006.01)
Patent
CA 2730981
The present invention provides a system, method and computer program for determining constraint errors in hardware design debugging. The invention may be included as part of a complete verification solution. The method involves applying a diagnostic technique such that under-constrained problems are identified by adding a model-free error suspect or error candidate on the primary input signals (or other signals where constraints or stimuli are usually added). The present invention also provides a system, method and computer program that enables hardware design correction, consisting of the use of generating correction waveforms for identifying one or more corrections at the gate level and/or logic level of the hardware design. A number of different diagnostic techniques can be used in this way for example, include simulation-based techniques, BDD-based techniques, SAT-based techniques and path tracing. The method described can be implemented as part of a debugging computer system or computer program, including an automated debugger. The method described herein can also be implemented into a design correction engine that is operable to generate correction waveforms for each of the under constrained signals to provide to a user or automated system or computer program deeper insight for under-constrained problems. Furthermore, under-constrained signals may be combined with one or more correction waveforms to provide a software fix or external fix to a fabricated chip by providing a value sequence that is operable to avoid an error or bug in the fabricated chip.
Safarpour Sean Arash
Smith Duncan Philip Norman
Veneris Andreas
Yang Yu-Shen
de Fazekas Anthony
Safarpour Sean Arash
Smith Duncan Philip Norman
Veneris Andreas
Vennsa Technology Inc.
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