Systems and methods for dynamic power savings in electronic...

Details Systems and methods for dynamic power savings in electronic... Systems and methods for dynamic power savings in electronic...

G - Physics

11

C

G11C 7/10 (2006.01) G11C 7/12 (2006.01) G11C 7/18 (2006.01) G11C 8/08 (2006.01) G11C 8/14 (2006.01)

Patent

CA 2720069

Power reduction is accomplished in an electronic memory by segmenting portions of the memory and only enabling certain memory portions depending upon where the memory is to be accessed. In one embodiment, the bit lines are segmented using latch repeaters to control address selection with respect to segments beyond a first segment. The latch repeaters are, in one embodiment, allowed to remain in their operated/non-operated state at the completion of a memory read/write cycle. This then avoids successive enabling pulses when the same segment is accessed on successive cycles.

Une réduction de puissance est obtenue dans une mémoire électronique en segmentant des parties de la mémoire et en ne validant que certaines parties de la mémoire en fonction des emplacements de mémoire devant faire lobjet dun accès. Dans un mode de réalisation, les lignes de bit sont segmentées en utilisant des répéteurs à bascule pour commander la sélection d'adresse en relation avec des segments au-delà d'un premier segment. Les répéteurs à bascule sont, dans un mode de réalisation, autorisés à rester dans leur état activé/non activé à la fin d'un cycle de lecture/écriture de mémoire. Cela évite ensuite la génération d'impulsions de validation successives lors dun accès au même segment pendant des cycles successifs.

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