Systolic array processing apparatus

Details Systolic array processing apparatus Systolic array processing apparatus

H - Electricity

01

Q

351/58

H01Q 21/08 (2006.01) G01S 3/28 (2006.01) G06F 7/50 (2006.01) H01Q 3/26 (2006.01)

Patent

CA 2010152

SYSTOLIC ARRAY PROCESSING APPARATUS Abstract of the Disclosure A rectangular antenna array includes a plurality of systolic vertical line arrays. Each vertical line array includes a plurality of signal processors. Within each line array, the signals received at any one moment are held or delayed as required, and the processors progressively form partial sums in an upward direction during first clock intervals and in a downward direction during alternate clock intervals. During each clock intervals, complete sums for one sample interval appear at an end of the vertical line array. The sums appear alternately at the top and the bottom of the line arrays. Beamforming in the horizontal direction is accomplished with systolic horizontal adders coupled to the tops and bottoms of the vertical line arrays. The horizontal adders transfer information and add in one direction during first clock intervals, and then in the other direction during third clock intervals of a four-interval cycle. In a particular embodiment of the invention, multiple inputs and outputs associated with each processor allows continued operation in the event of partial or complete failure of one or more processors.

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