Systolic computational array

Details Systolic computational array Systolic computational array

G - Physics

06

F

326/13, 354/141

G06F 17/15 (2006.01)

Patent

CA 1192315

ABSTRACT The present invention provides a systolic computational array including two shift registers. Selected ones of the shift register stages are adapted to provide the values contained therein to two multiply-accumulate devices. Some, but not all, of the stages of each shift register are adapted to provide the value contained therein to two multiply-accumulate devices. In this manner 2N-1 summations may be performed using two N stage shift registers. Thus fewer shift register stages are required, leading to a proportionate space saving. Additionally the system of the present invention requires less time to calculate a correlation because values may be loaded into consecutive shift register stages and all multiply-accumulate devices operate during every cycle.

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