Tapered mask method of semiconductor manufacture

Details Tapered mask method of semiconductor manufacture Tapered mask method of semiconductor manufacture

H - Electricity

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356/136

H01L 21/38 (2006.01) H01L 21/00 (2006.01) H01L 21/265 (2006.01) H01L 21/266 (2006.01) H01L 21/56 (2006.01) H01L 29/00 (2006.01) H01L 31/107 (2006.01)

Patent

CA 1071333

PHN 8222 ABSTRACT Method of manufacturing a semiconductor device, in particular a capacitance diode, a zener diode or an avalanche diode, by using only one masking step. According to the invention, a first masking layer, for example a silicon oxide layer, is provided on a substrate of one conductivity type the etching rate of which at the surface is increased, for example, by an argon bombardment. A second masking layer is provided on the first masking layer and a window is etched therein. Via said window a first zone preferably of the same conductivity type as the substrate is im- planted while using the second masking layer as a mask. The first masking layer is etched via the same window so that a bevelled edge is formed. By ion implantation via the window and a part of the bevelled edge, a second zone is formed which forms a p-n junction preferably with the first zone and the substrate.

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