G - Physics – 06 – F
Patent
G - Physics
06
F
354/230.85
G06F 9/46 (2006.01)
Patent
CA 1084628
TASK MANAGEMENT APPARATUS ABSTRACT A data processing system is described which has multi- ple sets of registers each of which is capable of autono- mously controlling a common storage and common arithmetic and logic control circuits to execute respective tasks of a program. Level status blocks (LSBs), each assigned to a respective task, are held in main storage; and each con- tains such address and status data as is required for task execution in a controlled environment. Apparatus, including a current level register, a selected level register, a pending level register and an in-process bit latch, is con- trolled during the execution of a load level status block (LLSB) instruction to transfer the LSB of a selected task from storage to the selected register set, determine the status of the in-process bit of the selected task LSB and the relative priority levels of the current and selected tasks, and pursuant to said two determinations handle the task dispatching, preemption, enqueuing, dequeuing functions without the need for further software processing. At the completion of the LLSB instruction execution, either the current task execution is continued, the selected task is initiated, a pending task is initiated or a system wait state is entered. A store level status block (STLSB) instruction is executed to copy the LSB of a selected task from the register set to storage. Hardware backup regis- ters are provided to -1- hold certain updated status of the current register set to improved performance. These backup registers are changed during the LLSB execution if task switching occurs and are restored to the current register set during STLSB execution. -2-
281861
International Business Machines Corporation
Na
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