Ternary logic circuits with cmos integrated circuits

Details Ternary logic circuits with cmos integrated circuits Ternary logic circuits with cmos integrated circuits

H - Electricity

03

K

328/125

H03K 19/00 (2006.01) G11C 11/40 (2006.01)

Patent

CA 1109127

TERNARY LOGIC CIRCUITS WITH CMOS INTEGRATED CIRCUITS Abstract of the Disclosure: Ternary storage elements are realized using ternary operators and fundamental circuits, designed to make practical use of CMOS (or COS/MOS) integrated circuits. Word-organized and trit-organized memory cells are designed for the construction of a ternary random-access-memory array (TRAM). Several flip-flops (tri-flops) are constructed and described in detail, including a PZN (set positive, set zero and set negative), a clocked PZN, a D-type and a T-type. Ternary shift registers and ring counters are formed by means of these tri-flops. A master-slave T-type tri-flop is used for the construction of a ternary up counter which is able to count from 0 to 3n using the normal ternary code or from -(3n-1)/2 to +(3n-1)/2 when the signed-ternary code is employed. With a little modification, a ternary down counter may also be constructed. A divide-by-M ternary counter which can be programmed is described. A ternary decoder and encoder are presented, which are the elements of a complete ternary read-only- memory (TROM). A modified ternary inverter (MTI) is taken as a unit cell of a ternary memory matrix.

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