Test circuit for differential cascode voltage switch

Details Test circuit for differential cascode voltage switch Test circuit for differential cascode voltage switch

G - Physics

06

F

324/58.1

G06F 11/26 (2006.01) G01R 31/28 (2006.01) G01R 31/3185 (2006.01) G06F 11/00 (2006.01) G06F 11/267 (2006.01)

Patent

CA 1229384

TEST CIRCUIT FOR DIFFERENTIAL CASCODE VOLTAGE SWITCH ABSTRACT An improved testing and checking circuit for a Differential Cascode Voltage Switch which uses N-devices for both the invalid (0,0) and (1,1) state detection of Q and ? switch signals, and uses decoupling pass devices for sampling the data at the fall of the system C-clock, additionally allowing simultaneous pre-charging and error detection. The testing and checking circuit is incorporated in a hierarchical scheme, which uses the system C-clock for input to the latches, decoupling of the buffers, and pulling up and down the error lines. The error fault is held in a system latch. Also described is a circuit scheme which self tests a large macro using only the C-clock and latches the result in a single latch. More particularly, the described circuit employs the Q and Q signals in a NOR configuration, thus detecting if neither signal has sufficient voltage to pull down the load device which consists of a P-device whose gate is attached to the C-clock. The resulting signal is run to a gate in parallel with the two N-devices. Thus, the two low signals allow this NOR gate to rise and produce a pulldown leg to an error line. An invalid signal condition is detected if either both signals are sufficiently high to turn on an N-device or neither signal is high enough to turn on an N-device. Therefore, the described circuit registers a failure if and only if there is the potential for a tree with the same inputs to enter an invalid state.

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