Test system for lsi circuits resident of lsi chips

Details Test system for lsi circuits resident of lsi chips Test system for lsi circuits resident of lsi chips

G - Physics

01

R

324/58.1

G01R 31/28 (2006.01) G01R 31/3185 (2006.01) G06F 11/00 (2006.01) G06F 11/27 (2006.01)

Patent

CA 1149874

Abstract of the Disclosure A test system performs dynamic testing of complex logic modules at full system clock rates and is resident on each LSI chip under test. The system logic is designed to be included on each LSI chip to reduce the time and computation required to detect and isolate faults in systems built from one or more chips. The on chip system includes switchable transmission gates to alter logic paths, a control shift register in the test function, an input shift register, an associated test generator and accumulater, an output shift register and an associated generator and accumulator. This logic provides test operands for the logic function under test and analyzes the resultant operands. Test operands are produced using a shift register connected to all inputs of the logic function under test. Checksum logic together with a shift register produce a running checksum of all output states of the module under test at the operative clock rate of the LSI.

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