Test technique for semiconductor memory array

Details Test technique for semiconductor memory array Test technique for semiconductor memory array

G - Physics

01

R

352/82

G01R 31/00 (2006.01) G01R 31/26 (2006.01) G11C 29/04 (2006.01) G11C 29/14 (2006.01) G11C 29/50 (2006.01)

Patent

CA 1048645

TEST TECHNIQUE FOR SEMICONDUCTOR MEMORY ARRAY Abstract of the Disclosure Disclosed is a technique for testing electronic storage arrays including bistable storage cells fabricated in accordance with integrated semiconductor technology. Also described is the testing of load devices in a flip flop storage cell which is connected to a pair of bit lines that are inaccessible for the direct application of test signals. Testing is performed by altering the time duration of signals applied to the memory cells under test.

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