Testing circuit

Details Testing circuit Testing circuit

G - Physics

01

R

G01R 31/28 (2006.01) F42C 21/00 (2006.01) G01R 31/02 (2006.01)

Patent

CA 2115960

ABSTRACT A testing circuit is provided for testing the operability both of a load and of a capacitor incorporated into a main detonator circuit and arranged to discharge into the load for detonation thereof. A test pulse is generated at a central controller to which a ring of detonators is connected on a harness. The test pulse is routed via the harness for storage in the capacitor. A controlled switch is operated to allow the capacitor to discharge into the load. A transistor is operated by the discharge signal, the transistor having an output for delivering a discharge value signal in response to the discharge signal falling below a threshold value. The discharge value signal is latched and is in turn used to inhibit a local oscillator. The inhibited signal from the oscillator is routed back to the controller so as to indicate a fault either in the capacitor or in the load.

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