Testing embedded arrays

Details Testing embedded arrays Testing embedded arrays

G - Physics

11

C

356/198, 352/82

G11C 29/00 (2006.01) G01R 15/12 (2006.01) G01R 31/3185 (2006.01) G11C 29/02 (2006.01) G11C 29/20 (2006.01)

Patent

CA 1038079

TESTING EMBEDDED ARRAYS Abstract An LSI semiconductor device includes a memory array incorporating address and data registers, and associated combinatorial and or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, the address registers and data registers are converted to counters by the addition of an EXCLUSIVE OR circuit to two or more positions of the register. The address and data registers are stepped through all of their states. The data register counter outputs may then be compared with the array outputs, thereby allowing one to check address selection as well as the ability to write or read at each of the storage locations.

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