Testing embedded arrays

Details Testing embedded arrays Testing embedded arrays

G - Physics

11

C

356/198, 352/82

G11C 29/00 (2006.01) G01R 15/12 (2006.01) G01R 31/3185 (2006.01) G11C 29/48 (2006.01)

Patent

CA 1048646

TESTING EMBEDDED ARRAYS Abstract A large scale integrated (LSI) chip or semiconductor device includes a memory array and associated logic circuitry. The array is "embedded" in the sense that it is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing there is added to the device gating means to the memory array and wiring extending from primary access points of the device to the memory array bypassing and in parallel with the logic circuitry. The device further includes control means operatively associated with the gating means for switching the input to the array between the logic circuitry and the primary access points. In the latter condition direct access to the array is permitted, thereby facilitating testing.

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