H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/128
H01L 29/94 (2006.01)
Patent
CA 1199427
- 1 - Abstract: A three-dimensional semiconductor device is constructed in which MOS transistors are arranged, not only in the direction of the substrate surface, but also in a direction perpendicular thereto. At least one layer of insulator film and of single-crystal film are stacked alternately and deposited on a surface of a semiconductor substrate. An impurity-doped region formed in each semiconductor film is used as a gate, source or drain of a MOS transistor. The arrangement provides a device that has a higher integration density than heretofore available.
431117
Haruta Ryo
Kimura Shinichiro
Miyao Masanobu
Mukai Kiichiro
Nishioka Yasushiro
Hitachi Ltd.
Kirby Eades Gale Baker
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