Three gate non-volatile memory cell

Details Three gate non-volatile memory cell Three gate non-volatile memory cell

G - Physics

11

C

356/128, 352/82.

G11C 11/40 (2006.01) G11C 17/00 (2006.01) H01L 29/792 (2006.01)

Patent

CA 1196419

THREE GATE NON-VOLATILE MEMORY CELL ABSTRACT OF THE DISCLOSURE A non-volatile memory cell of reduced size is disclosed for use in a semiconductor memory. The cell includes first and second gates insulated from a silicon substrate to form a pair of MOS transistors. A storage transistor is formed by a third gate which is disposed between the other two gates and which is insulated from the substrate by material suitable for forming a storage transistor with the third gate. Preferably, a drain region is disposed in the substrate adjacent to the first gate and a source region is disposed in the sub- strate adjacent to the second gate. Thus, the second gate can isolate the storage transistor from the source region to permit the source to be coupled to other cells in the same row and thereby act as a common source for an entire row of cells.

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