Time dependent master reset

Details Time dependent master reset Time dependent master reset

G - Physics

05

F

323/6

G05F 1/46 (2006.01) H02H 3/247 (2006.01) H03K 17/16 (2006.01) H03K 17/22 (2006.01)

Patent

CA 1134439

TIME DEPENDENT MASTER RESET Abstract of the Disclosure A circuit for use with logic circuitry pre- venting any transients due to the power down and power up conditions of a power supply from causing any false or random operations of the logic. The turn off tran- sients are suppressed by a reset signal to the logic circuitry generated by a timing module which is trig- gered when it detects an absence of AC signal over a specified period of time and is then held in a reset mode until the power supply voltage completely decays. The turn on transients are suppressed by a reset signal to the logic circuitry generated by the timing module, which is held in a reset. mode until the power supply voltage has stabilized.

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