Timing control in semiconductor memory systems

Details Timing control in semiconductor memory systems Timing control in semiconductor memory systems

H - Electricity

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H03K 19/08 (2006.01) G11C 11/4076 (2006.01) H03K 3/01 (2006.01) H03K 5/05 (2006.01) H03K 5/06 (2006.01) H03K 5/14 (2006.01)

Patent

CA 1039851

TIMING CONTROL IN SEMICONDUCTOR MEMORY SYSTEMS Abstract of the Disclosure Apparatus for precisely controlling the interval by which a conditioning signal on one conductor overlaps part of a unit enabling signal on another conductor in a dynamic storage semiconductor memory system. The apparatus provides an initial conditioning signal pulse which extends beyond the desired interval of overlap with the unit enabling timing pulse and gates the conditioning signal with a selectively delayed inverse of the unit enabling pulse. This provides a resultant conditioning or precharging timing pulse that terminates at the end of a precise interval after the leading edge of the associated unit enabling timing pulse.

206448

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