Timing delay equalization circuit

Details Timing delay equalization circuit Timing delay equalization circuit

H - Electricity

04

L

328/28

H04L 7/00 (2006.01) H03L 7/087 (2006.01) H03L 7/14 (2006.01) H04J 3/06 (2006.01) H04L 1/22 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 1212153

- 28 - TIMING DELAY EQUALIZATION CIRCUIT Abstract A circuit for generating a common signal as a function of either of two reference signals comprises a pair of phase-locked loops which share an oscillator. Each phase-locked loop generates a control signal as a function of one of the reference signals. One or the other of the control signals is coupled to the oscillator which generates the common signal. A comparator compares the two control signals and generates a signal indicative of their difference. While the control signal generated by the first phase-locked loop is coupled to the oscillator, the difference signal is applied to the second phase-locked loop where it controls the generation of the second control signal to minimize the difference between the two control signals. While the control signal generated by the second phase-locked loop is coupled to the oscillator, the second phase-locked loop is nonresponsive to the difference signal. Thus when a switch of reference signals occurs even if they are of different phase and even if that phase is slowly time-varying, the circuit can lock to the new reference signal at a phase dictated by the phase difference between the two references at the instant of the switch without causing the oscillator output to undergo significant frequency or phase changes.

433568

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