Timing recovery for variable bit-rate video on asynchronous...

H - Electricity – 04 – L

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H04L 7/02 (2006.01) H04L 12/56 (2006.01) H04N 7/52 (2006.01) H04N 7/62 (2006.01)

Patent

CA 2146801

The problems associated with slow timing recovery in an ATM receiver are overcome by detecting the transmission rate of a received bit stream and periodically detecting the transmitted Enc_CR values, which are used to calculate additional estimated clock reference (Est_CR) values between the actual transmitted Enc_CR values. The Est_CR values are then used along with the actually received Enc_CR values to generate a phase locked loop (PLL) error signal (TC_ERROR), wherein the PLL is caused to converge more rapidly. In one embodiment, the TC_ERROR values are generated for each received cell or packet instead of only for each received Enc_CR value and, consequently, timing recovery is significantly speeded up. Additionally, the Est_CR values can be adjusted to minimize the effects of lost cells, as well as, drift in the transmission rate.

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