H - Electricity – 04 – L
Patent
H - Electricity
04
L
H04L 29/02 (2006.01) H04L 12/24 (2006.01)
Patent
CA 2277422
A method and apparatus for allocating master priority to a unique one of a plurality of interconnected processors. A data storage register is provided for each processor. The registers and processors are interconnected to enable any processor to store data in all of the registers, and to enable each processor to read data stored in that processor's register. A unique multiple bit identifier is allocated to each processor. The processors are synchronized with one another, and master priority is arbitratively allocated to the processor having the lowest value identifier. The arbitration involves repetitively, for each processor which, has not previously been dismissed as a "master" candidate: ~ storing a predefined dismissal value in the processor's register; ~ selecting a next portion of the processor's identifier; ~ if the selected portion of the identifier has a value corresponding to a predefined non-dismissal value, actuating the processor to store the non-dismissal value in all of the registers; and, ~ if the selected portion of the identifier has a value corresponding to the dismissal value and if the non-dismissal value is stored in the processor's register, dismissing the processor as a "master" candidate; until all but one of the processors are dismissed as a "master" candidate.
Alexander Thomas
Smith Matt
Oyen Wiggs Green & Mutala Llp
Pmc-Sierra Inc.
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