Transistor fabrication methods and methods of forming...

Details Transistor fabrication methods and methods of forming... Transistor fabrication methods and methods of forming...

H - Electricity

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H01L 21/336 (2006.01) H01L 21/266 (2006.01) H01L 21/8244 (2006.01) H01L 27/11 (2006.01) H01L 29/786 (2006.01)

Patent

CA 2149538

2149538 9413009 PCTABS00032 Transistor fabrication methods are provided for transistors with current carrying elements above a semiconductor substrate. Only few mask alignments define critical dimensions such as the channel length of a MOS transistor. In one embodiment, where the channel region (154) overlies the gate (110), a first mask (126) is formed over the channel region (154), and an LDD implant is carried out. A second mask (158) is formed over the LDD portion of the drain region (150). The second mask (158) is allowed to extend over the first mask (126). A heavy doping implant is carried out. An LDD structure is provided on the drain but not on the source side with only the first mask (126) defining the channel length (134). In some embodiments, both masks include photoresist. The first photoresist mask (126) is hardened to prevent its lifting during development of the resist of the second mask (158).

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