Transistor fault tolerance method and apparatus

Details Transistor fault tolerance method and apparatus Transistor fault tolerance method and apparatus

H - Electricity

03

K

328/198, 323/6

H03K 17/08 (2006.01) H03K 17/082 (2006.01)

Patent

CA 1276993

Transistor Fault Tolerance Method and Apparatus Abstract A power transistor control circuit for controlling the bias input to the power transducer. During normal operations two switching transistors bias the base input to a power transistor positively and negatively to turn the power transistor on and off. By back biasing a conducting transistor, however, the blocking voltage capability of the transistor is diminished. To maintain blocking voltage at a maximum, the present circuit senses overcurrent conditions indicating a problem condition exists and turns off the power transistor by neutrally biasing a base input. Preferably, both switching tran- sistors used to bias the base input during normal opera- tion of the transistor are rendered nonconductive to accomplish this neutral biasing.

502542

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