Translation look aside buffer with parallel exception...

Details Translation look aside buffer with parallel exception... Translation look aside buffer with parallel exception...

G - Physics

06

F

354/239

G06F 12/10 (2006.01) G06F 12/14 (2006.01)

Patent

CA 2029628

Abstract An apparatus and method for translating virtual addresses to physical addresses of a main memory is dis- closed. The main memory includes a plurality of pages, each page of memory corresponds to a page address. The virtual addresses are stored in a content addressable memory. The content addressable memory includes a plurality of entries and each entry contains one of the virtual addresses. The random access memory includes a plurality of entries and each entry of the random access memory contains one of the page addresses and associated with each page address is access privilege information. The access privilege informa- tion denotes the level of authorization required for access- ing the page associated with the requested page address from main memory. Each entry of the random access memory corre- sponds to an entry of the content addressable memory. Asso- ciated with each entry of the content addressable memory and associated with each corresponding entry of the random access memory is a means for performing a predetermined logic function for comparing said access privilege for one of said pages of said main memory with access privilege for the request and determining whether the requested access privilege is sufficient for accessing the page of main memory.

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