Translator lookahead controls

Details Translator lookahead controls Translator lookahead controls

G - Physics

06

F

354/239

G06F 12/02 (2006.01)

Patent

CA 1078069

TRANSLATOR LOOKAHEAD CONTROLS ABSTRACT OF THE DISCLOSURE Lookahead circuits for an address relocation translator containing stacks of segmentation registers (SR's), each of which may be loaded with an assigned address of a physical block in a main memory. An additional pair of bit positions are provided with each SR to receive lookahead bits from decoder loading circuits which, decode a physical address being loaded into the SR to indicate the storage unit containing the addressed block. During each subsequent address translation, the loaded lookahead bits are outgated while the block address is being read from the SRX. The lookahead bits are decoded for selecting the required storage unit, and a translator interface is switched to that unit. The lookahead bits are handled by parallel high-speed circuits which operate faster than the larger circuits handling the block address being read from the SR. As a result, the required storage unit is selected before a storage unit cycle is generated by the translator for accessing the addressed block.

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