Transmission system for the synchronous digital hierachy

H - Electricity – 04 – L

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H04L 1/00 (2006.01) H04J 3/06 (2006.01)

Patent

CA 2064602

PHD 91.051 13.03.1992 ABSTRACT: Transmission system for the synchronous digital hierarchy. The invention relates to a transmission system for the synchronous digital hierarchy comprising at least one adaptation circuit for compensating for phase variations of a STM-N signal. The adaptation circuit (8) comprises for insertingjustification locations for at least one container of the STM-N signal a buffer (17, 51), a write address generator (16, 53), a read address generator (18, 61), a justification decision circuit (24, 60) and an output circuit (19, 62). The buffer is provided for feeding container data and for reading container data. The write address generator is intended for forming write addresses for the data to be written and the read address generator for forming read addresses for the data to be read out. In a first solution the justification decision circuit is used for forming a justification signal from the combination of difference values of the addresses of the read and write address generators and low-pass filtered values from values which contain the justification information of the container data to be written. In a second solution the justification decision circuit is used for forming low-pass filtered difference values from the addresses of the read and write address generators and for forming a justification signal from the low-pass filtered difference values. The output circuit is used for forming negative or positive justification locations in the container in response to the justification signal and for forming an output signal from the data stored in at least one buffer. Fig. 7.

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