Tri-state bussing system

Details Tri-state bussing system Tri-state bussing system

G - Physics

06

F

354/226

G06F 11/00 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1149068

ABSTRACT This relates to an apparatus and method for providing an accurate data group to the instruction buffer of a data pro- cessing system. The data group is simultaneously applied to the instruction buffer and to the error correcting apparatus. After analysis of the data group in the error correcting ap- paratus, the operation in progress is aborted if an error has been detected, and the error is not correctable. If correctable, the correct instruction data group is applied to the execution unit. If no error is detected in the data group, utilization of the data group proceeds uninterrupted. Two, three state busses are employed. The first three state bus is used to transmit memory data to the error detection and correction (EDAC) circuitry, to transmit corrected data from the (EDAC) circuitry and to the data output circuits and to transmit input data to the memory. The second three state bus transmits data to the instruction buffer, to the EDAC circuitry and also transmits corrected data from data output circuits to the instruction buffer.

326834

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