Tri-well cmos technology

Details Tri-well cmos technology Tri-well cmos technology

H - Electricity

01

L

356/179

H01L 29/06 (2006.01) H01L 21/38 (2006.01)

Patent

CA 1239707

TRI-WELL CMOS TECHNOLOGY Richard C. Joy Tarsaim Lal Batra ABSTRACT A semiconductor structure having at least three types of wells which may be of different doping levels and methods of manufacturing such a structure, are disclosed. In one method, regions which will become active devices are protected with a nitride layer as the associated well-regions are implanted. In another method, previously implanted wells are covered with thick oxide which in combination with the nitride layer provides automatic alignment of adjacent wells. In yet another method, implanted wells are covered with oxide while a last well is implanted with this last well being defined by both thick oxide and photoresist. All methods avoid a masking step and avoid the need for aligning the edge of a later photoresist mask with the edge of an earlier photoresist mask. The structures formed by these methods may have heavily-doped P wells, heavily-doped N wells, and lightly- doped P or N wells, or both, for forming higher breakdown voltage devices on the same chip with lower breakdown voltage devices.

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