Tristate logic circuits

Details Tristate logic circuits Tristate logic circuits

H - Electricity

03

K

328/158

H03K 19/088 (2006.01) H03K 5/02 (2006.01) H03K 19/013 (2006.01) H03K 19/082 (2006.01)

Patent

CA 1196698

- 15 - ABSTRACT IMPROVEMENTS IN OR RELATING TO TRISTATE LOGIC CIRCUITS A power-down network is included in a tristate TTL circuit to reduce power dissipation in the high impedance third state while permitting high switching speeds during bistate operation of the circuit. The power-down network includes a power-down transistor (T6) connected in series between the collector resistor (R1) and collector of the phase splitter transistor (T2). The base of the phase splitter transistor is connected through a diode (D1) to a disabling gate (106). When the circuit is in the high impedance state, the power- down transistor is turned off to interrupt current flow through the collector resistor and substitute a relatively high impedance current path through a resistor (R7) to the disabling gate for the relatively low impedance current path through the collector resistor.

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