True single error correction system

Details True single error correction system True single error correction system

G - Physics

06

F

354/223

G06F 11/00 (2006.01) G06F 11/10 (2006.01)

Patent

CA 1184308

TRUE SINGLE ERROR CORRECTION SYSTEM Abstract A scheme for true error correction and multiple bit failure detection for a memory system using multiple data bits per chip. An H-Matrix results in syndrome generation of bits that are unique for single bit failures that will not match syndromes generated by multiple bit failures. All multiple bit failures are detected without miscorrecting any single bits that have not failed. Single pass logic employs all syndromes in parallel inputs to determine the presence of a single bit failure for subsequent correction and also detects the presence of multiple bit failures.

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