Ttl/cmos compatible input buffer

Details Ttl/cmos compatible input buffer Ttl/cmos compatible input buffer

H - Electricity

03

K

328/128, 328/193

H03K 19/094 (2006.01) H03K 3/3565 (2006.01) H03K 19/003 (2006.01) H03K 19/0185 (2006.01) H03K 19/0948 (2006.01)

Patent

CA 1267196

TTL/CMOS COMPATIBLE INPUT BUFFER Hung-Cheng Hsieh ABSTRACT A TTL/CMOS compatible input buffer includes an input inverter and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage to the source of the P-channel transistor in the inverter having a magnitude which forces the trigger point of the input inverter to assume a preselected value. Typically the preselected value is selected to be 1.4 volts in order to maximize the input noise margins. A second stage input inverter introduces hysterisis to improve the noise immunity of the system The reference voltage generator includes an operational amplifier connected to a voltage divider network. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to power supply voltage is provided to the input inverter. As the result, the trigger point of input inverter is higher than 1.4 volts which provides a larger input noise margin. The voltage divider network and the operational amplifier are powered down so that no DC power is consumed.

518485

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