Ttl to cmos input buffer

Details Ttl to cmos input buffer Ttl to cmos input buffer

H - Electricity

03

K

328/128, 328/130

H03K 19/094 (2006.01) H03K 17/10 (2006.01) H03K 19/00 (2006.01) H03K 19/0185 (2006.01)

Patent

CA 1252521

TTL TO CMOS INPUT BUFFER Abstract A TTL to CMOS input buffer is disclosed which prevents static current flow when the TTL input signal is at a relatively low voltage logic "1" state. A transition detector (44) responsive to the input TTL logic signal and a voltage boosting circuit (50) connected between a positive power supply (VDD) and the input to a first CMOS inverter (30) are utilized to sense an input signal "0" to "1" transition and boost the TTL logic "1" signal to a voltage level which will prevent the p-channel transistor (32) included in the CMOS inverter from turning "on". The voltage boosting circuit is subsequently disconnected from the input to the p-channel transistor to prevent the input from being fully charged to the positive power supply. (FIG. 3)

510067

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