Two-way examining frame synchronization circuit

H - Electricity – 04 – L

Patent

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Details

H04L 7/04 (2006.01) H04J 3/06 (2006.01) H04L 1/20 (2006.01) H04L 7/08 (2006.01)

Patent

CA 2251822

A frame synchronization circuit is disclosed, which prevents the occurrence of synchronous error due to a data loss/insertion while restraining a false synchronization/out of synchronization based on typical code error in a conventional data transmission system. The frame synchronization circuit is provided with a frame synchronization code detector which detects a frame synchronization code from a received data sequence to output a frame position and outputs a checked result by checking a frame synchronization code detected and a correct frame synchronization code, and a data loss and data insertion period judgement circuit which presumes whether a data loss or data insertion has occurred in the received data sequence according to the checked result.

L'invention concerne un circuit de synchronisation de trames qui ne provoque pas de désynchronisation résultant de la disparition/insertion de données, tout en supprimant la mauvaise synchronisation/l'asynchronisme provoqué(e) par des erreurs de code de représentation de systèmes de transmission de données classiques. Ce circuit de synchronisation de trames comprend un circuit de détection (32) qui détecte un code de synchronisation de trames dans une séquence de données reçue, et produit une position de trame et des résultats de collationnement, par collationnement du code de synchronisation de trames détecté. Ce circuit de synchronisation de trames comprend également un circuit d'évaluation (54) qui évalue si des données ont disparu ou ont été insérées dans la séquence de données reçue, sur la base des résultats de collationnement.

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