G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 13/00 (2006.01) G06F 13/14 (2006.01) G06F 13/40 (2006.01) H04L 12/42 (2006.01) H04L 12/43 (2006.01)
Patent
CA 2159453
A high speed data collection processing and distribution system (Fig. 1) for coupling a plurality of digital data sources (16, 22) to a plurality of digital data processors (13, 19, 20). The system (Fig. 1) includes a plurality of segmented parallel data paths (DPS1, DPS2, DPS3, DPSn) and a plurality of nodes (Node-1, Node-2, Node-3, Node-n) connecting said parallel data paths (DPS1, DPS2, DPS3, DPSn) in an endless ring. Each node (Node- 1, Node-2, Node-3, Node-n) includes an input connector (IPC2) for connecting the end of one of said segments of parallel data paths (DPS1) on a one-for-one basis; a data multiplexer (31-2), a plurality of node parallel data paths (NPDS2) in the node (Node-2) corresponding to the segmented parallel data paths (DPS1), respectively, connected to the input connector of the data multiplexer (31-2) such that data input to the multiplexer (31-2) corresponds to respective ones of the segmented parallel data paths (DPS1). A control processor (32-2) is coupled to said node parallel data paths (NPDS2), and a second input of the processor (31-2). A common source clock (30) and slot signals (CSC1, CSC2, CSC3, CSCN) is independently connected to said control processor (32-1, 32-2) in each node, respectively, for controlling the timing thereof. Each node also includes transmit (53) and receive FIFO (43) buffer memories address (44), exclusive source (45) and pattern matching (46) circuits and a local clock distribution circuit (40).
Connor Glenn
Davis Virgil
Krone Norris
Pierson Roger
Na
University Research Foundation Inc.
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