Undesirable modulation reduction of deflection circuit

Details Undesirable modulation reduction of deflection circuit Undesirable modulation reduction of deflection circuit

H - Electricity

04

N

350/104

H04N 3/16 (2006.01)

Patent

CA 1087304

UNDESIRABLE MODULATION REDUCTION OF DEFLECTION CIRCUIT Abstract Of The Disclosure In a switched vertical deflection circuit, two SCR switches couple horizontal retrace pulses to a capacitor. A modulator couples pulse width modulated gating pulses to the SCR's. The SCR's couple to the capacitor successively smaller portions of the horizontal retrace pulses during a first part of the vertical trace interval and successively larger portions during a second part for developing in a vertical deflection winding a sawtooth vertical deflection current. The modulator couples gating pulses to one of the SCR's during the vertical retrace interval for substantially loading the horizontal deflection circuit during the vertical retrace interval for preventing undesired oscillations within the horizontal deflection circuit. - 1 -

277733

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