Unidirectional looped busses microprocessor

Details Unidirectional looped busses microprocessor Unidirectional looped busses microprocessor

G - Physics

06

F

354/237

G06F 9/00 (2006.01) G06F 13/32 (2006.01) G06F 13/42 (2006.01)

Patent

CA 1091359

UNIDIRECTIONAL LOOPED BUSSES MICROPROCESSOR ARCHITECTURE Abstract A computing system architecture includes a central processing unit having a channel, arithmetic and logic unit, a plurality of working registers, and control logic; a plurality of local storage registers; a main storage; an executable control store; one or more input/output devices; and a multiplexed cycle steal and interrupt request common poll bus. The storage and input/output devices communicate with and are controlled by the central processing unit over a looped, or unidirec- tional bus and control channel including a bus in, which is returned as a bus out, a six-bit code bus, and a plurality of control lines. Bus out is operated to address the executable control store and main storage, and to provide data to the input/output devices and the local storage registers. Bus in is shared by the input/output devices and all storage devices and registers for transferring data and control information to the central processing unit. Bus in is also used by main storage to receive data from the input/output de- vices and from the local storage registers. The six-bit code bus addresses the input/output devices and the local storage registers, thus enabling overlapping of device or local storage data transfers with the accessing of executable control storage and main storage, and with instruction execution. The arithmetic and logic unit is time shared for data and input/ output processing, register/register and storage/register transfers, shift operations, byte manipulations address modifications, and pro- gram counter incrementing. Both cycle steal and interrupt requests are received by the central processor on the common poll bus. -1-

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