Universal protocol data receiver

Details Universal protocol data receiver Universal protocol data receiver

H - Electricity

04

L

354/222

H04L 1/00 (2006.01) H04L 12/56 (2006.01)

Patent

CA 1252898

- 1 - Abstract: A universal protocol data receiver is disclosed which is capable of receiving data streams in character mode and block mode, providing flow control and error detection and correction. The receiver is divided into two stages, separated by a first-in, first-out buffer register. The first stage handles flow control and error processing as well as initialization. The second stage handles interfacing with the data utilizing mechanism and flow control acknowledgements. The FIFO buffer is divided into two parts by a movable barrier which limits the access of the second stage. The barrier permits error processing by hiding incoming blocks of data behind the barrier until processing is complete. Both a hardware and a software implementation of the receiver are disclosed.

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