V-mos device with self-aligned multiple electrodes

Details V-mos device with self-aligned multiple electrodes V-mos device with self-aligned multiple electrodes

H - Electricity

01

L

356/126, 352/40

H01L 29/78 (2006.01) H01L 21/768 (2006.01) H01L 27/108 (2006.01) H01L 29/423 (2006.01)

Patent

CA 1159953

ABSTRACT V-MOS Device with Self-Aligned Multiple Electrodes High density VMOSFET devices, particularly single transistor memory cells, are provided by use of series of simplified self-aligning process steps. Gate electrodes, source/drain regions and source/ drain contacts are provided with the aid of an initial mask-less photoresist removal process in which a relatively thick layer of self-leveling photoresist is uniformly removed in order to define portions of a gate electrode within the recess of a V-groove. The gate electrode subsequently acts as a self-aligned mask to define implanted source/ drain regions also within the V-groove and to enable second level interconnecting metallurgy contacts to be formed along the sidewalls of the V-groove. BU-978013

377171

Affiliated with

Also associated with

Rating

V-mos device with self-aligned multiple electrodes does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with V-mos device with self-aligned multiple electrodes, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and V-mos device with self-aligned multiple electrodes will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-339494