H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/149, 328/200
H01L 27/02 (2006.01) H01L 29/06 (2006.01)
Patent
CA 1322231
Abstract VDD LOAD DUMP PROTECTION CIRCUIT The present invention provides power supply load dump protection circuitry for insuring that supply voltages that are applied to the supply pad of a low current logic circuit and which exceed a preselected voltage level are prevented from damaging the logic circuit and also from appearing at an output of the logic circuit. Three circuit areas are protected. An integrated 5V regulated supply circuit is protected by connecting the supply pad to a polysilicon resistor in series with the source of the p-channel MOS output pull up transistor of the regulator circuit, the drain of the driver being connected to the 5V regulated supply pad. 16V low current logic circuits associated with the input pads, output pads and the 5V regulator are protected by connecting the supply pad to a large value polysilicon resistor in series with the power supply pads of these circuits. 16V high current output signal circuits are protected by connecting the supply pad to the source of the p-channel MOS output pull up transistor of the output circuit, with its drain being connected to the output pad. Each of the p-channel MOS transistors has its gate connected to a detection circuit which, upon detection of load dump transients, turns them off. All of the above-described transistors and resistors, are designed to withstand maximum load dump transients.
576051
Miller William E.
National Semiconductor Corporation
Smart & Biggar
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