Validity checking arrangement for extended memory mapping of...

Details Validity checking arrangement for extended memory mapping of... Validity checking arrangement for extended memory mapping of...

H - Electricity

04

Q

354/224, 344/29,

H04Q 3/54 (2006.01) G06F 11/00 (2006.01) H04Q 3/545 (2006.01)

Patent

CA 1217846

A VALIDITY CHECKING ARRANGEMENT FOR EXTENDED MEMORY MAPPING OF EXTERNAL DEVICES ABSTRACT OF THE DISCLOSURE In a telecommunications switching system, a CPU utilizes memory mapped access to a number of duplex external devices and other memories. A validity checking arrangement provides for detecting invalid external device unit numbers for memory mapped accesses by the CPU. In addition, this validity checking arrange- ment will determine that the CPU's operating software has attempted a memory mapped access with an invalid unit number or that a true hardware fault exists.

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