Variable access frame buffer memory

Details Variable access frame buffer memory Variable access frame buffer memory

G - Physics

09

G

354/237

G09G 1/16 (2006.01) G09G 5/393 (2006.01)

Patent

CA 1253976

31 Abstract A frame buffer memory comprises a set of memory chips arranged in an array of n rows (planes) and m columns. All memory chips are iden- tically addressed, a set of m, n-bit pixels being stored at each memory address with one bit of each pixel being stored in each array plane. Each memory chip of each column is row address strobed by a common row address strobe line while each memory chip of each plane is column address strobed by a common column address strobe line. By appro- priately strobing selected row and column address lines, data may be written to the memory array on a pixel-by-pixel or plane-by-plane basis with such data being written to individual pixels or planes or to blocks of pixels or planes. Combinational logic within the frame buffer memory permits pixel data to be rapidly modified according to preselec- ted rules during a memory write operation prior to being written into memory.

504375

Affiliated with

Also associated with

Rating

Variable access frame buffer memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Variable access frame buffer memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable access frame buffer memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1203761