Variable clamped memory cell

Details Variable clamped memory cell Variable clamped memory cell

G - Physics

11

C

352/81

G11C 11/40 (2006.01) G11C 8/08 (2006.01) G11C 11/411 (2006.01) G11C 11/415 (2006.01)

Patent

CA 1282493

ABSTRACT OF THE DISCLOSURE An improved memory cell circuit in which the collector of the "ON" transistor is clamped to a variable voltage level to prevent saturation. Saturation is prevented by providing a mechanism for limiting the voltage between a first node in the word line circuit and the collector of the conducting transistor to a first level, while limiting the voltage between the first node and the collector of the nonconducting transistor to a second, lower level. In one embodiment, clamping transistors have their emitters coupled to the collectors of the memory cell transistors and their bases coupled to the word line. A common resistor couples the load resistors of a plurality of memory cells to the word line. In a second embodiment, the common resistor couples the bases of the clamping transistors to an intermediate node in a Darlington driver for the word line.

539045

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