Variable-length bit data processing circuit and method

Details Variable-length bit data processing circuit and method Variable-length bit data processing circuit and method

H - Electricity

03

M

H03M 7/40 (2006.01) G06F 5/01 (2006.01) H03M 7/42 (2006.01)

Patent

CA 2177722

A variable bit-length code processing circuit includes first, second and third registers (12, 20, 22) each of which is of 1 word, and memory data is loaded to the first register (12), and a variable bit-length code is withdrawn from the third register (22). The second register (20) and third register (22) are coupled to a barrel shifter (16) which barrel-shifts data of 2 words according to a barrel shift amount which is applied by a subtracter (30) on the basis of the number of the valid bits and the number of the remaining bits.

Un circuit de traitement de données binaires de longueur variable comprend des premier, second et troisième registres à un mot (12, 20, 22). Des données provenant d'une mémoire sont chargées dans le premier registre (12), et des données binaires de longueur variable sont extraites du troisième registre (22). Les second et troisième registres (20, 22) sont couplés à un bloc fonctionnel de décalage circulaire (16) qui décale deux mots de données en fonction de données de volume de décalage circulaire basé sur le nombre de bits effectifs et de bits restants obtenu par un soustracteur (30).

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