Variable phase bit sampling with minimized synchronization loss

Details Variable phase bit sampling with minimized synchronization loss Variable phase bit sampling with minimized synchronization loss

G - Physics

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G01D 3/032 (2006.01) G01D 5/247 (2006.01) G01R 29/02 (2006.01) H03K 5/19 (2006.01) H03K 21/40 (2006.01) H04L 1/00 (2006.01) H04L 7/033 (2006.01)

Patent

CA 2495135

Variable phase bit sampling implementations minimize requirements for downstream digital processing resynchronization in adjustable bit phase sampling systems utilizing variable delay elements which can interrupt the clocking stream signal. A sampling device includes a sampling circuit having data input, clock input, and an output signal in response to a data signal. A variable delay circuit adjustably triggers the clock input in response to a first delay control signal. A fixed delay circuit delays the output signal by a predetermined amount in response to a delay control signal. By implementing the sampling device, a system clock signal may be connected directly to a downstream digital processing circuit. Thus, a potentially corrupted clock stream from the variable delay element is connected only to the data sampling device, and a fixed delay section that can be programmatically inserted between the sampling device output and the input to the downstream digital processing device.

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