Variable rate clock signal recovery circuit

Details Variable rate clock signal recovery circuit Variable rate clock signal recovery circuit

H - Electricity

04

L

325/72

H04L 7/00 (2006.01) G11B 20/14 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1060548

ABSTRACT A circuit for use in a digital data receiver to recover a clock signal, of variable rate, from the signal received by the receiver. A typical digital data receiver includes demodulating or other means for converting the received signal to a binary data signal having a characteristic which changes in a manner corresponding to transitions in the digital data received. The invention provides circuit means for recovering a clock signal from the binary data signal where the data rate may vary over a substantial range. The clock signal recovery circuit utilized a logic transition detector to produce a narrow pulse at each data transition in the binary data signal. The pulses, which contain harmonic frequencies at the clock rate of the binary data signal, are up-converted or mixed with an electrical signal from a frequency synthesizer. The signal resulting from this up-conversion is filtered by a narrow-band filter to produce an electrical signal at a pre- determined intermediate frequency. The output signal from the frequency synthesizer is mixed with the signal from the narrow-band filter, in a down-convertor circuit, to produce a reference signal having a frequency proportional to the clock frequency of the binary data signal. The frequency synthesizer has a variable frequency output determined by the setting of a data rate selector. An electronically controlled oscillator produces a signal having a frequency proportional to the binary-data-signal clock rate. The oscillator is in a phase- lock loop including a phase detector supplied with the reference signal having a frequency proportional to the clock rate of the binary data signal.

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