Variable wordlength computing module for dataflow processors

G - Physics – 06 – F

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354/232, 354/67

G06F 9/44 (2006.01) G06F 9/30 (2006.01)

Patent

CA 1258129

- ? - "Variable Wordlength Computing Module for Dataflow Processors" ABSTRACT OF THE DISCLOSURE A computing module for a dataflow processor converts a variable wordlength code into a series of first and second half-wordlength codes of higher and lower significant bits and appends an identifying indicator or label to each half-wordlength code. A half-to-full word converter sequentially receives the half-wordlength codes and combines them into a full-wordlength code in response to the receipt of the indicator appending to the second half-wordlength code. A queuing circuit detects a full-wordlength code of later arrival from the half-to-full word converter means which forms with a full-wordlength code of early arrival from the converter a data set necessary to effect computations and simultaneously sending the full-wordlength codes of early and later arrivals to a computing logic, which effects the computations on the full-wordlength codes and produces a full-wordlength code indicating the result of the computations. A full-to-half word converter divides the full-wordlength code obtained by the computing logic into half-wordlength codes and appending an identifying indicator to each of the divided half-wordlength codes.

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