Vectored interrupts in a cathode ray tube display

G - Physics – 06 – F

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Details

375/46, 354/230.

G06F 3/153 (2006.01) G06F 13/34 (2006.01) G09G 1/16 (2006.01)

Patent

CA 1134049

ABSTRACT A cathode ray tube display terminal system includes a central processor subsystem and a number of peripheral subsystems which are all coupled in common to a system bus. Apparatus in the central processor subsystem receives interrupt request sig- nals from the peripheral subsystems and on a predetermined prior- ity basis modifies an address generated by the central processor subsystem. The modified address, called a vectored address, points to a firmware subroutine stored in a memory subsystem, also coupled to the system bus, which processes the selected interrupting peripheral subsystem. Other peripheral subsystems coupled to the system bus generate a single Interrupt signal which is applied to the apparatus in the central processor system. The highest prior- ity peripheral subsystem generating the single interrupt signal responds to an interrupt acknowledge signal by sending address signals to the apparatus for generating the vectored address.

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