Vernier addressing apparatus

Details Vernier addressing apparatus Vernier addressing apparatus

G - Physics

11

C

354/241

G11C 8/00 (2006.01) G01S 7/292 (2006.01) G06F 1/035 (2006.01) G06F 7/00 (2006.01)

Patent

CA 1191275

VERNIER ADDRESSING APPARATUS Abstract A vernier address scale reduces the number of addressable memory locations required for numerical look-up tables. Read- only memories (ROMs) store the data of linear or non-linear functions. Decoders determine which ROM is selected and advantage is taken of accuracy improvement as numbers become larger by dropping least significant bits as the vernier address scale moves from one ROM table to another. Accuracy is further improved by using a method of one-half level quantization step for rounding. This reduces the size of numerical tables for math processing of reciprocals, roots of numbers, powers of numbers, logarithms, trigonometric and exponential functions.

430428

Affiliated with

Also associated with

Rating

Vernier addressing apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Vernier addressing apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vernier addressing apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1299784