Vertical trench transistor/capacitor memory cell

Details Vertical trench transistor/capacitor memory cell Vertical trench transistor/capacitor memory cell

H - Electricity

01

L

356/25

H01L 21/82 (2006.01) H01L 21/205 (2006.01) H01L 21/8242 (2006.01) H01L 27/108 (2006.01) H01L 29/78 (2006.01)

Patent

CA 1289266

Y09-87-022 VERTICAL TRENCH TRANSISTOR/CAPACITOR MEMORY CELL ABSTRACT OF THE DISCLOSURE A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate and an epitaxial layer thereon including a vertical transistor disposed in a shallow trench stacked above and self-aligned with a capacitor in a deep trench. The stacked vertical transistor 14 has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor is a lightly-doped drain structure connected to a bitline element. The source of the transistor, located at the bottom of the transistor trench and on top of the center of the trench capacitor, is self-aligned and connected to polysilicon contained inside the trench capacitor. Three sidewalls or the access transistor are surrounded by thick oxide isolation and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well and uses the n-well and heavily-doped substrate as the capacitor counter-electrode plate. The cell storage node is the polysilicon inside the trench capacitor and include steps for growing epitaxial layers wherein an opening is left which serves as the shallow trench access transistor region and provides self-alignment with the deep trench storage capacitor.

571409

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