Very high speed error detection network

Details Very high speed error detection network Very high speed error detection network

H - Electricity

04

L

340/74

H04L 1/00 (2006.01) H03M 13/09 (2006.01)

Patent

CA 2010134

ABSTRACT OF THE DISCLOSURE A very high speed cyclic redundancy code (CRC) generator/tester used to implement a CRC polynomial for purposes of detecting errors in telecommunications data. A given n-bit word message to be transmitted over some medium is first processed by the very high speed CRC generator/tester in order to generate, in parallel format, a cyclic redundancy code word to be attached to said message. The n-bit word message plus cyclic redundancy code word is then processed, in a manner identical to processing at transmitter, at the receiver in order to establish if a transmission error has occurred. The parallel processing offered by this very high speed CRC generator/tester allows for much greater processing speeds than the prior art.

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